Design & Verification Engineer Staff- Semiconductor (LSI)

<Number of employees : Total : 21 Local : 19 Japanese : 2 >
<Report Line : Vietnamese project leader>
<Team Member: 2-3 persons>
<Number of Subordinates: 0 persons>
<Products: LSI design, IoT solution development>
<Clients: Domestic and Japanese Company(Japan, Singapore, Taiwan, China, USA) >
<Saturday Working: None>

<Job Responsibilities>
With the specifications required by the customer as INPUT
Carry out specific design verification work using the following languages

**OUTPUT
Functional specifications (English)
Implementation specifications (English)
RTL (Verilog / SystemVerilog)
Verification strategy (English)
Verification item table (English)
Verification environment construction / verification scenario (System Verilog / SVA / UVM / C)
Verification environment manual (English)
Verification result report (English)
- Other tasks assigned by manager

<Necessary Skill / Experience >
- Age : 23 - 30
- Gender : Any
- More than 2 years experience as engineer in semiconductor industry, having skill as below;
*Front-end design and verification of ASIC
*RTL design by Verilog HDL/VHDL
*Design and verification using a general-purpose bus AMBA(AXI/AHB/APB)
*Assertion-Based Verification
- Technician who can do task by himself/herself

<Preferable Skill / Experience>
- English skill : Business level(overseas business trip, meeting with overseas engineers)
- Technical sill as below
Design and verification of ASIC built-in CPU
Design and verification of high-speed interfaces such as PCI Express and USB
Random verification using SystemVerilog
Testbench building that was applied verification methodology(UVM)

<Schedule>
- Joining date : Negotiable
- Interview round : 1-2 times
1st interview :
1.1 Free discussion with QnA (30 minutes – 1 hour)
2nd interview : Second day or same day after above result is OK
2.1 CMEV introduction (10 minutes)
2.2 Presentation of the result at past Pj by candidate (15 minutes)

VietnamHo Chi Minh Map

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