Tóm tắt công việc
Nghề | Nghề yêu cầu kỹ thuật (Bán hàng, Thiết kế, Phát triển, Quản lý sản xuất)/Phát triển, Nghiên cứu, Thực nghiệm, Quản lý dự án |
---|---|
Ngành | Ngành khác/ |
Hình thái tuyển dụng | Chưa phân loại |
Chức vụ | Khác |
Số lượng tuyển dụng | 1 người |
Ngày muốn vào làm | - |
Kỹ năng ngôn ngữ cần thiết |
Tiếng Nhật (Giao tiếp kinh doanh) Tiếng Anh (Giao tiếp kinh doanh) |
Ngôn ngữ có thể sử dụng | - |
Thời gian làm việc | Khác |
Ngày nghỉ / Phúc lợi y tế |
Chi tiết công việc
<Position Objective/Expectation>
・This position will work in Japan for 2 years and then return to Vietnam.
・The candidate will be trained in Vietnam for about 3 months before going to Japan,
・Expected to gain the trust of our clients and be active as a team leader in charge of projects upon your return to Vietnam.
<Job Responsibilities>
・Perform the following design and verification tasks based on the "Requirement specifications" received from the customer.
・Creating those documents in English
- Functional specifications, Implementation specifications
- Verification strategy, Verification item table.
・Constructing verification environment, verification Scenario using below
- RTL(Verilog and System Verilog) or HLS(SystemC, C, C++)
- System Verilog, SVA, UVM, C
・Creating those documents in English
- Verification environment manual
- Verification result report
・Other tasks assigned by the manager
<Necessary Skill / Experience >
- More than 2 years experience as an engineer in the semiconductor industry, having skills as below;
*Front-end design and verification of ASIC
*RTL design by Verilog HDL/VHDL
*Design and verification using a general-purpose bus AMBA(AXI/AHB/APB)
*Assertion-Based Verification
- Technician who can do tasks by himself/herself
- Language skill: Business level in Japanese or English (overseas business trip, meeting with overseas engineers)
<Preferable Skill / Experience>
- Technical skills as below
Design and verification of ASIC built-in CPU
Design and verification of high-speed interfaces such as PCI Express and USB
Random verification using SystemVerilog
Testbench building that applied verification methodology(UVM)
<Schedule>
- Joining date: Negotiable
- Interview round: 1-2 times
1st interview :
1.1 Free discussion with QnA (30 minutes – 1 hour)
2nd interview: The second day or the same day after the above result is OK
2.1 CMEV introduction (10 minutes)
2.2 Presentation of the result at past Pj by the candidate (15 minutes)
Về cuộc phỏng vấn